Assessment Details and Submission Guidelines
Unit Code BE102 – T2 2017
Unit Title Digital Systems
Assessment Type Group, written
Assessment Title Assignment2: Arithmetic Logic Unit (ALU) and Random Access Memory (RAM)
Purpose of the assessment (with ULO Mapping) This assignment provides students with sound knowledge of the principles and practices of digital systems, both at the device and circuit level. Students will be able to perform some of the digital system concepts such as number systems, logic gates, combinatorial and sequential logic circuit design. This assignment is designed to apply the theoretical concepts of digital analysis to integrated electronic applications
Weight 15% of the total assessments
Total Marks 65
Due Date Week 11, submit report on Moodle
Submission Guidelines • All work must be submitted on Moodle by the due date along with a completed Assignment Cover Page.
• The assignment must be in MS Word format, 1.5 spacing, 11-pt Calibri (Body) font and 2 cm margins on all four sides of your page with appropriate section headings.
• Reference sources must be cited in the text of the report, and listed appropriately at the end in a reference list using IEEE referencing style.
Extension • If an extension of time to submit work is required, a Special Consideration Application must be submitted directly to the School's Administration Officer, on academic reception level. You must submit this application within three working days of the assessment due date. Further information is available at:
• Academic Misconduct is a serious offence. Depending on the seriousness of the case, penalties can vary from a written warning or zero marks to exclusion from the course or rescinding the degree. Students should make themselves familiar with the full policy and procedure available at: http://www.mit.edu.au/about-mit/institute-publications/policies-procedures-and-guidelines/Plagiarism-Academic-Misconduct-Policy-Procedure. For further information, please refer to the Academic Integrity Section in your Unit Description.
Part B: Design/Implementation of Random Access Memory (RAM) – Sequential Logic
RAM is a device to which binary information is transferred for storage and a device from which stored binary information is retrieved.
You are required to design a 8x2 bit Random Access Memory (RAM) device. i.e. each of the 8 addresses are capable of storing 2 bit information and stored information should be available for retrieval.
Basic memory cell diagram is given:
You need to use Logisim software tool to display your implementation/design and for demonstration.
Your submission should include the following steps:
I. All truth tables and expressions for combinational logic, Karnaugh maps, minimizations, wherever appropriate
II. Description of the design
III. Implementation using Logisim
IV. Demonstration (Addressing, reading from an address and writing to an address)
Section to be included in the report Description of the section Marks
Introduction Brief introduction to the reports 5
Part A Building an 8-bit Arithmetic Logic Unit (ALU) – Combinational logic 25
Design/Implementation of Random Access Memory (RAM) – Sequential Logic
Grades Excellent Very Good Good Satisfactory Unsatisfactory
Introduction Concise and specific to the exercise Topics are relevant and soundly analysed. Generally relevant and analysed. Some relevance and briefly presented. This is not relevant to the assignment topic.
Part A Concise and specific to the case study Topics are relevant and soundly analysed. Generally relevant and analysed. Some relevance and briefly presented. This is not relevant to the assignment topic.
Part B Concise and specific to the case study Topics are relevant and soundly analysed. Generally relevant and analysed. Some relevance and briefly presented. This is not relevant to the assignment topic.