Recent Question/Assignment

Swinburne University of Technology
Faculty of Science Engineering and Technology
Mini Project 2
Design of Dynamic RAM Controller
Design a simplified and shared dynamic RAM controller circuit which has the following specifications: (Use two different coding styles)
Design a simplified synchronous dynamic RAM controller which provides to a host a bus like interface. The figure below illustrates a typical block diagram connection. The SDRAM controller generates a busy output which the host can use as handshake control. This avoids the need of fixed wait states. The SDRAM controller has the following specifications:
The inputs are a 16 bit address (ADDRIN), a read signal (RD), a write signal (WR), and an enable signal (CS) generated by a host core. The controller does not function until CS becomes 1, then a 16-bit ADDRIN is loaded in as a row address ( 15 down to 8) and a column address ( 7 down to 0) registers. Also RD and WR signals are registered and the busy signal “Ready” is sent to the Host. Subsequently, the row address is outputted at ( ADDROUT) along with the row address strobe (RAS) signal which is generated one clock cycle later. Then, the column address is outputted along with the column address strobe signal (CAS) which is generated one clock cycle later. Finally, if the operation is a read operation ( RD = 1, WR = 0), then the RE output is 1. Otherwise, for a write operation ( RD = 0, WR = 1), the RE output remains 0. If both RD and WR are 1 or 0, the controller terminates the memory access operation. Write a VDHL model for the SDRAM controller
Your submission should include
1. A technical paper report written using IEEE format (refer to attached paper for guidelines). This paper should discuss the design DRAM controllers strategies, types and relate it to the internal structure of the DRAMs.( you need to research this and summarize the technical information and compare this design to other strategies)
2. The paper should have an appendix which includes
? Source code and test bench files along with waveforms & comments added to verify the functionality of design.
? Synthesis results and the estimated maximum speed of the circuit using 3 different state assignment methods.( for each design)