Recent Question/Assignment

attached is the assignment i need all parts completely done just do the write up and attach screenshots of the schematic and simulations and write a little about what you did.
2016 EECS 170D Project 1.
Due October 17, 2016
The primary goal of this project is for you to become familiar with the Cadence VLSI design environment, including schematic capture, layout, LVS (layout vs. schematic comparison), DRC (design rule checking) and simulation.
Here, you need to implement a small digital CMOS circuit, namely the sum portion of an adder (A XOR B XOR C).
To do (the “requirements”):
• Get Cadence up and running with the NCSU library (see instructions in the setup guide on our web page). Note that there are many high-­-quality tutorials on this sort of process out there in cyberspace (google “cadence tutorial”), e.g. this one:
o http://www.ece.virginia.edu/~mrs8n/cadence/Cadencetutorials.html
• Enter the schematic of the CMOS cell, starting from scratch (don’t just load a circuit you find in a library). You must use all four transistor terminals (i.e., the bulk connection too). Include labels.
• Simulate the cell using SPICE from within Cadence starting from the extracted schematic.
• Make a layout of the cell. You must include well(s) and well contacts, labels, etc.
• Perform LVS to verify that the schematic and layout match perfectly. You must check transistor sizes as well as mere connectivity.
• Perform DRC to check that you have not violated any layout design rules.
• Simulate the circuit again, starting from the extracted layout (not the schematic), noting any differences. Rules of the road:
• You may work individually or in teams of two.
• You may use examples in the book as guidelines. Please do not use examples that you find on-­-line, from other class projects, from libraries, etc.
• Students and teams are on their honor to perform their own design work, e.g., layout, simulations, etc., start to finish.
• An exception: You are encouraged to ask for help from other teams with issues concerning setting up Cadence, how to perform certain tasks in Cadence such as LVS, and other tool-­-related problem-­-solving. Please DO be nice and try to help other teams with these issues. I will thank you, as will your classmates.
Submission:
• Submit your project in PDF form (one submission per team, not one per person), typed, with explanations and plenty of supporting figures, screenshots of results, etc., to demonstrate the success of all of the above “to do” items.
• Style counts! Students often discount how important the quality of their written work can be. I do care about this, just as “the real world” will, so make sure your project reports are well-­-written and look professional.
• Don’t worry about grades, just focus on performing and demonstrating the above tasks and developing a clear, professional-­-looking report.